In certain integrated circuits it is required to fabricate a capacitor in series with the gate. The latter is usually made of polysilicon and needs to be heavily doped with a donor material in order to reduce its resistivity. This is commonly achieved by using POCl.sub.3 (phosphorus oxychloride) as a diffusion source. Doping in this manner means subjecting the polysilicon gate pedestal to temperatures as high as 950.degree. C. for as long as 15 minutes.
In FIG. 1 we show a schematic view of a capacitor of this type. Source and drain regions 3 and 4 are formed within silicon body 2. Spanning the gap between 3 and 4 is a layer of gate oxide 5 above which is a heavily doped polysilicon pedestal that serves as the gate electrode. Dielectric layer 7 lies atop layer 6 and conductive layer 8 is the counter electrode for the capacitor structure that has thus been formed. Although shown here as a single layer, 7 is often a hybrid of more than one material. For example it could be composed of a layer of silicon oxide topped by a layer of silicon nitride. Regardless of what dielectric material is being used, if there are rough spots on upper surface 9 of poly gate 6, these will act as local high field points at which premature dielectric breakdown will occur.
Polysilicon is normally deposited by CVD (chemical vapor deposition) using silane as the silicon bearing gas. Deposition takes place at about 630.degree. C. Associated with this relatively high temperature is considerable grain growth. This is not, of itself, a problem but, as already mentioned above, the polysilicon gate pedestal still has to undergo POCl.sub.3 doping. During the latter procedure, grains of different crystal orientation react somewhat differently to the incoming phosphorus atoms. The net result is a surface that, on a microscale, is quite rough. This roughness (which we measure in Angstroms) is defined by using an AFM (Atomic Force Microscope).
As already noted above, if at least one surface of the capacitor's electrodes is rough, the breakdown voltage of the resulting structure will be lower than is achievable with the materials being used. For example, curve 21 of FIG. 2 is a plot of capacitor leakage current as a function of applied voltage across a capacitor whose lower polysilicon electrode was prepared as described above. The dielectric was 4400 Angstroms thick. Breakdown was defined to have ocurred when the leakage current reached 1 microamp. The breakdown voltage V.sub.B was 60 volts.
Prior art in this area appears to have been focussed on increasing the capacitance per unit area of the capacitors rather than on raising the breakdown voltage. Thus, Zahurak et al. (U.S. Pat. No. 5,639,685 June 1997) disclose a method for increasing the roughness of a polysilicon surface by depositing a thin layer of amorphous silicon onto it and then annealing between about 350.degree. and 600.degree. C. in the presence of a dopant bearing gas. This causes the amorphous silicon to crystallize into hemi-spherical grain polysilicon which leads to an increase in surface area which in turn means a larger capacitance per unit area when a dielectric layer and counter-electrode are deposited over it.
Hayashide et al. (U.S. Pat. No. 5,290,729 March 1994) is similar to Zahurak et al. in that its purpose is also to increase the effective surface area of a capacitor and they achieve this by depositing polysilicon under conditions close to the transition conditions from amorphous to polycrystalline. Lou et al. (U.S. Pat. No. 5,597,754 January 1997) is similar. Increased capacitance is achieved by forming a hemispherically grained surface of polysilicon for the lower electrode. Dennison et al. (U.S. Pat. No. 5,663,090 September 1997) also teach how hemispherical grain silicon may be used as a capacitor electrode.
Chou (U.S. Pat. No. 5,286,668 February 1994) describes a capacitor that is in series with the drain and is located alongside the gate pedestal. By shaping it so that the lower electrode extends upwards and outwards from the drain a capacitor that overhangs the gate is formed. Several different polysilicon layers are used as part of the process.